Services | Huxiaowei

Module Navigation

Start from your scenario, then align scope, definitions, and deliverables during the first call.

IC Design

Custom IC/SoC, IP integration, sign-off verification, and tape-out support.

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Data Intelligence

Chip Data Intelligence

Yield analytics (YAE), reliability & predictive maintenance—governance and consistent metrics included.

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Smart EDA

Design knowledge base, assistive intelligence, and standardized flows for faster convergence.

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Chip + Data

Chip + Data Solutions

Co-delivery of hardware and data, with observability and continuous improvement loops.

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IC Design Services

Custom delivery for Fabless, OEM/system companies, and research projects—driven by engineering processes for quality and traceability.

Scope

Custom IC design: from spec definition and architecture to RTL implementation and physical design—end-to-end or module-by-module.

SoC system design & integration: subsystem integration, HW/SW co-design and verification, with production-oriented project discipline.

IP licensing & integration: evaluation, licensing coordination, integration, and tailoring (subject to authorization and compliance review).

Key Capabilities & Acceptance-ready Deliverables

Verification & sign-off: front-end simulation, FPGA prototyping, back-end sign-off (timing/power/physical, as applicable), and issue closure.

Tape-out support: stage-based checklists, documentation readiness, and milestone confirmation—plus full-cycle coordination and technical support.

Typical deliverables (examples): specifications, architecture docs, verification plans & coverage reports, sign-off reports, version/change logs, and tape-out preparation checklists.

              Public disclosure principle: we do not publish client confidential information or sensitive implementation details. Controlled or sensitive topics are discussed only after NDA signing and compliance review.
            

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Data Services (for Chip Design & Manufacturing)

Governance first—then build sustainable intelligence loops around yield, reliability, and full lifecycle operations.

Capability Modules

Yield analytics & improvement (YAE): identify key factors from manufacturing-test data and wafer electrical parameters, and close the loop with actionable recommendations.

Predictive maintenance & reliability: build models from in-field runtime and fault data to optimize reliability and lifecycle management.

Governance & definitions: metric definitions, data quality, master data, access control, and audit to ensure usable, trustworthy, and traceable data.

Delivery Path & Compliance Notes

Implementation path: scenario selection (pilot) → data inventory & authorization → governance & definitions → analytics/modeling → dashboards & workflow embedding → iteration.

Deliverables (examples): metric definition docs, data dictionary & lineage, masking rules, analysis reports, model evaluation reports, operations playbook, and alert/closure workflows.

              Compliance reminder: client data must be authorized; sensitive data follows minimization; performance metrics are disclosed only under auditable definitions.
            

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Design Flow Optimization & Smart EDA

Turn historical design data into reusable knowledge, then introduce assistive intelligence in an explainable, verifiable way.

Capability Modules

Design data mining & knowledge base: structure historical project data into searchable best practices and reusable templates.

Assistive intelligence: predictive insights and optimization suggestions for intermediate results (place/route, timing convergence, power hotspots, etc.), validated via PoC.

Flow standardization: checkpoints, review gates, and version management to improve cross-team efficiency and traceability.

Deliverables & Risk Control

Deliverables (examples): knowledge-base IA, labeling & quality standards, evaluation metrics, toolchain integration guidance, pilot validation reports, and retrospectives.

Outcome statement principle: no guaranteed uplift claims—benefits are evaluated via baselines and reproducible definitions.

              Security reminder: design data is highly sensitive by default; we apply least privilege, masking, and audit trails.
            

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Integrated Offering: Chip + Data Solutions

For products and system applications, we co-deliver custom chips with data collection/analytics and algorithm optimization for an end-to-end loop.

Typical Scenarios

Design custom data-processing chips for end customers, with post-deployment data collection, analytics, and algorithm optimization services.

Typical scenarios: edge intelligence, equipment condition monitoring, reliability loops, data-driven product iteration, and operations optimization.

Delivery focus: clear interfaces, consistent data definitions, production observability, and accountable issue handling.

Compliance Prerequisites & Delivery Boundaries

Data compliance: define collection scope, purpose, retention, and sharing boundaries before kickoff; sign DPA and NDA as needed.

Security requirements: configure access control, audit logs, encryption, and backups to meet MLPS 2.0 and client security requirements.

              Disclosure principle: client cases and impact data require authorization and masking; sensitive technical details are not disclosed on public pages.
            

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Compliance & Security Notice

          We follow the Cybersecurity Law, Data Security Law, and Personal Information Protection Law (PIPL) and implement data minimization, purpose limitation, consent/authorization, and auditable logging.
          Public website content does not include client confidential information or controlled sensitive technical details. Sensitive information is exchanged only after NDA signing and compliance review.
        

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Delivery Standards & Boundaries

Before kickoff we align deliverables, communication cadence, and boundaries to reduce collaboration friction.

Typical Deliverables List

Deliverables vary by service type. Below are common examples.

Service Type	Phase Outputs	Final Outputs
IC/SoC design	Spec clarifications, architecture review notes	Design delivery package (per contract)
Sign-off & tape-out	Verification plan, issue tracking & closure	Sign-off reports, tape-out checklist
Chip data analytics & platform	Metric definitions, dictionary & masking rules	Analytics/model reports, operations playbook
Smart EDA & flow optimization	Pilot plan, baseline definitions	Validation report, reuse & rollout checklist
Integrated (chip + data)	Joint specification & data compliance assessment	Architecture, go-live and operations loop

Communication & SLA

Routine requests are responded to within 1 business day. Urgent items can be handled via an agreed fast-track process.

During the project we assign a fixed communication owner and (by default) run bi-weekly progress syncs with risk notes.

Deliveries follow a submit → confirm → revise → archive workflow to ensure version traceability.

              Boundary statement: we do not provide services beyond what laws/regulations allow, what the client authorizes, or what the contract defines.
            